has anybody here worked with the oregano systems 8051 ip core. I
need help testing the parameterized number of timers on fpga. the
lines from the user guide document are here:"In the VHDL source file mc8051_p.vhd the constant C_IMPL_N_TMR
can take
values from 1 to 256 to control this feature. Values out of this
interval result in a non
functioning configuration of the core."
can someone explain how to access these new peripherals in the
keil source code th
↧