Hello,
Driver: CMSIS I2C STM32F4xx, Rev 2.3
The Driver produces an error after a 2-byte Master Receive
Operation.
After a 2-byte master Receive Operation I2C_CR1_POS bit remains
set.
A following master receice operation with more than 2 Bytes will
Crash.
The closing of the receive progress is faulty due to the POS bit.
No NACK is generated. (A deadlock is possible if the last bit of read
data was zero.
In this case the slave device holds sda low, waiting for clock
pulse
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