Dear All,
I'm trying to understand a system which is separated by I-RAM and
D-RAM as the below,
https://community.arm.com/cfs-file/__key/communityserver-discussions-components-files/10/pastedimage1514364784286v3.png
I want to know what kind of firmware-works things need to copy L2
boot to I-RAM ? what does it purpose for? even I want to know how
I-code and D-code work in Cortex M3 in point of view in Memory and
Linker Scripts in especially kind of separated I and D cache
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